@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: FX493 |Applying initial value "00000000" on instance cmd_reg[7:0] 
@N: FX493 |Applying initial value "0000" on instance main_state_back[3:0] 
@N: FX493 |Applying initial value "00000000" on instance byte_send_out[7:0] 
@N: FX493 |Applying initial value "0000000000000000000000000000000000000000000000000000000000000000" on instance temp[63:0] 
@N: MO225 :"c:\users\test\desktop\calculator_lcd\jlx12832g_lcd.v":158:0:158:5|There are no possible illegal states for state machine clk_div_state[3:0] (in view: work.JLX12832G_lcd(verilog)); safe FSM implementation is not required.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: FX1056 |Writing EDF file: C:\Users\TEST\Desktop\calculator_lcd\impl1\calculator_lcd_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
